High-Performance Metal/High-$k$ n- and p-MOSFETs With Top-Cut Dual Stress Liners Using Gate-Last Damascene Process on (100) Substrates

Abstract

Newly proposed mobility-booster technologies are demonstrated for metal/high-k gate-stack n- and pMOSFETs. The process combination of top-cut SiN dual stress liners and damascene gates remarkably enhances local channel stress particularly for shorter gate lengths in comparison with a conventional gate-first process. Dummy gate removal in the damascene gate process induces high channel stress, because of the elimination of reaction force from the dummy gate. PFETs with top-cut compressive stress liners and embedded SiGe source/drains are performed by using atomic layer deposition TiN/HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate stacks with T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inv</sub> =1.4 nm on (100) substrates. On the other hand, nFETs with top-cut tensile stress liners are obtained by using HfSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> gate stacks with T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">inv</sub> =1.4 nm. High-performance n- and pFETs are achieved with I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> =1300 and 1000 muA/mum at I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">off</sub> =100 nA/mum, V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dd</sub> =1.0 V, and a gate length of 40 nm, respectively.