K. Tai

Novel Channel-Stress Enhancement Technology with eSiGe S/D and Recessed Channel on Damascene Gate Process

J. Wang, Y. Tateshita, Shuji Yamakawa et al. · 2007 · 27 citations

Engineering, Electrical Engineering, Electronic Materials +11

High-Performance and Low-Power CMOS Device Technologies Featuring Metal/High-k Gate Stacks with Uniaxial Strained Silicon Channels on (100) and (110) Substrates

Y. Tateshita, J. Wang, K. Nagano et al. · 2006 · 25 citations

Engineering, Electrical Engineering, Materials Science +17

High-Performance Metal/High-$k$ n- and p-MOSFETs With Top-Cut Dual Stress Liners Using Gate-Last Damascene Process on (100) Substrates

Satoru Mayuzumi, Shinya Yamakawa, Y. Tateshita et al. · IEEE Transactions on Electron Devices · 2009 · 23 citations

Engineering, Electrical Engineering, Materials Science +15

Extreme High-Performance n- and p-MOSFETs Boosted by Dual-Metal/High-k Gate Damascene Process using Top-Cut Dual Stress Liners on (100) Substrates

Satoru Mayuzumi, J. Wang, Shuji Yamakawa et al. · 2007 · 18 citations

Engineering, Electrical Engineering, Materials Science +13

A study for 0.18 /spl mu/m high-density MRAM

Mizuki Motoyoshi, I. Yamamura, W. Ohtsuka et al. · 2004 · 16 citations

Natural Sciences, Electrical Engineering, Materials Science +10