C. Kerner

Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession

T. Chiarella, Liesbeth Witters, A. Mercha et al. · Solid-State Electronics · 2010 · 120 citations

Electrical Engineering, Physical Design (Electronics), Engineering +8

The device architecture dilemma for CMOS technologies: Opportunities & challenges of finFET over planar MOSFET

Bertrand Parvais, A. Mercha, Nadine Collaert et al. · 2009 · 39 citations

Low-power Electronics, Electrical Engineering, Different Trade-offs +14

Stress Memorization Technique—Fundamental Understanding and Low-Cost Integration for Advanced CMOS Technology Using a Nonselective Process

C. Ortolland, Yasutoshi Okuno, Peter Verheyen et al. · IEEE Transactions on Electron Devices · 2009 · 31 citations

Engineering, Vlsi Design, Maskless Smt Integration +16

Experimental evidence of short-channel electron mobility degradation caused by interface charges located at the gate-edge of triple-gate FinFETs

J. Ramos, E. Augendre, Anil Kottantharayil et al. · 2006 · 30 citations

Device Modeling, Electrical Engineering, Abnormal Degradation +14

Strain Enhanced nMOS Using <i>In Situ</i> Doped Embedded $\hbox{Si}_{1 - x}\hbox{C}_{x}$ S/D Stressors With up to 1.5% Substitutional Carbon Content Grown Using a Novel Deposition Process

Peter Verheyen, Vladimir Machkaoutsan, Matthias Bauer et al. · IEEE Electron Device Letters · 2008 · 30 citations

Materials Science, Semiconductors, Electrical Engineering +15