D. Chidambarrao

Comparison of raised and Schottky source/drain MOSFETs using a novel tunneling contact model

M. Ieong, P. M. Solomon, S.E. Laux et al. · 2002 · 188 citations

Engineering, Electrical Engineering, Microelectronics +16

Dual stress liner for high performance sub-45nm gate length SOI CMOS manufacturing

Haining Yang, R. Malik, Y. Li et al. · 2005 · 142 citations

Engineering, Electrical Engineering, Manufacturing Engineering +11

High performance 14nm SOI FinFET CMOS technology with 0.0174µm ² embedded DRAM and 15 levels of Cu metallization

C-H. Lin, B. Greene, J. Cai et al. · 2014 · 129 citations

Engineering, Computer Engineering, Electrical Engineering +9

Strain effects on device characteristics: Implementation in drift-diffusion simulators

J.L. Egley, D. Chidambarrao · Solid-State Electronics · 1993 · 94 citations

Engineering, Electrical Engineering, Physics +16

High performance 65 nm SOI technology with dual stress liner and low capacitance SRAM cell

E. Leobandung, H. Nayakama, D. Mocuta et al. · 2005 · 65 citations

Engineering, Computer Engineering, Electrical Engineering +17