DrGaN: an Integrated CMOS Driver-GaN Power Switch Technology on 300mm GaN-on-Si with E-mode GaN MOSHEMT and 3D Monolithic Si PMOS

Abstract

We demonstrate industry’s first CMOS "DrGaN" technology fabricated in a 300mm GaN-on-Silicon process combining enhancement-mode high-k dielectric GaN MOSHEMT with integrated 3D monolithic Si PMOS by layer transfer. The 180nm DrGaN with power transistor width of 421.1mm achieves an excellent R <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf> = ImΩ (R <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DSON</inf> =0.8 mfl-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ) and drain leakage well below 0.1mA. In this work, we demonstrate a truly gate-last 3D monolithic integration process, where the high temperature activation steps for the Si PMOS transistors are completed before the gate dielectric of the GaN MOSHEMT transistors is deposited. This resolves one major hurdle in the 3D monolithic integration of GaN and Si CMOS transistors. Moreover, in this new process, the GaN and Si CMOS transistors share the same backend interconnect stack for reduced mask count and no additional intra-connects. The best FOM=1/(R <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</inf> Q <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GG</inf> ) of 0.59 (mΩ-nC) <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> is achieved for a L <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</inf> 30nm GaN MOSHEMT.