Impact of Gate Length and Doping Variation on the DC and Analog/RF Performance of sub - 3nm Stacked Si Gate-All-Around Nanosheet FET

Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET

N. Loubet, Terence B. Hook, P. Montanini et al. · 2017 · 988 citations

Engineering, Electrical Engineering, Microelectronics +15

FinFET scaling to 10 nm gate length

Bin Yu, Leland Chang, Safayet Ahmed et al. · 2003 · 595 citations

Engineering, Electrical Engineering, Microelectronics +15

Scaling theory for double-gate SOI MOSFET's

Ken Suzuki, Tetsu Tanaka, Y. Tosaka et al. · IEEE Transactions on Electron Devices · 1993 · 556 citations · Full text

Engineering, Electrical Engineering, Electronic Materials +16

High performance fully-depleted tri-gate CMOS transistors

B.S. Doyle, Suman Datta, M. Doczy et al. · IEEE Electron Device Letters · 2003 · 453 citations

Engineering, Electrical Engineering, Microelectronics +15

Calculated threshold-voltage characteristics of an XMOS transistor having an additional bottom gate

T. Sekigawa, Yutaka Hayashi · Solid-State Electronics · 1984 · 366 citations

Engineering, Electrical Engineering, Microelectronics +12