ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005. · 2005 · 37 citations · 14 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignDevice CharacterizationDevice ModelingDevice ScalingIntegrated Circuit DesignShort-channel EffectsBias Drift AnalysisBias Temperature InstabilityDevice VariabilityLeakage Current ModelingRobustness Against Random VariationsScaling Effects In CmosTransistor-level Leakage Analysis
6T-SRAM cells in the sub-100 nm CMOS generation are now being exposed to a fatal risk that originates from large local Vth variability (/spl sigma//sub v/spl I.bar/Local/). To achieve high-yield SRAM arrays in presence of random /spl sigma//sub v/spl I.bar/Local/ component, we propose worst-case analysis that determines the boundary of the stable Vth region for the SRAM read/write DC margin (Vth curve). Applying this to our original 65 nm SPICE model, we demonstrate typical behavior of the Vth curve and show new criteria for discussing SRAM array stability with Vth variability.
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