Hirofumi Shinohara

A divided word-line structure in the static RAM and its application to a 64K full CMOS RAM

Masahiko Yoshimoto, Keiko Anami, Hirofumi Shinohara et al. · IEEE Journal of Solid-State Circuits · 1983 · 167 citations

Engineering, Vlsi Design, Vlsi Static Rams +19

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

S. Ohbayashi, Makoto Yabuuchi, Koji Nii et al. · IEEE Journal of Solid-State Circuits · 2007 · 150 citations

System On Chip, Electrical Engineering, Local Variability +10

An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture

Hiroshi Makino, Y. Nakase, Hajime Suzuki et al. · IEEE Journal of Solid-State Circuits · 1996 · 134 citations

Low-power Electronics, Hardware Security, Electrical Engineering +12

A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment

Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto et al. · 2008 · 110 citations

Hardware Security, Non-volatile Memory, Electrical Engineering +13

A 373-F² 0.21%-Native-BER EE SRAM Physically Unclonable Function With 2-D Power-Gated Bit Cells and VSS Bias-Based Dark-Bit Detection

Kunyang Liu, Min Yue, Xuan Yang et al. · IEEE Journal of Solid-State Circuits · 2020 · 70 citations

373-F² 0.21, Non-volatile Memory, Electrical Engineering +12