Y. Nakase

An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture

Hiroshi Makino, Y. Nakase, Hajime Suzuki et al. · IEEE Journal of Solid-State Circuits · 1996 · 134 citations

Low-power Electronics, Hardware Security, Electrical Engineering +12

Leading-zero anticipatory logic for high-speed floating point addition

Hajime Suzuki, H. Morinaka, Hiroshi Makino et al. · IEEE Journal of Solid-State Circuits · 1996 · 109 citations

Fadd Core, Logic Synthesis, Real Data Type +12

A 600-MHz 54×54-bit multiplier with rectangular-styled Wallace tree

N. Itoh, Y. Naemura, Hiroshi Makino et al. · IEEE Journal of Solid-State Circuits · 2001 · 50 citations

Electrical Engineering, Physical Design (Electronics), Engineering +14

0.5 V Start-Up 87% Efficiency 0.75 mm² On-Chip Feed-Forward Single-Inductor Dual-Output (SIDO) Boost DC-DC Converter for Battery and Solar Cell Operation Sensor Network Micro-Computer Integration

Y. Nakase, Shinichi Hirose, Hiroshi Onoda et al. · IEEE Journal of Solid-State Circuits · 2013 · 28 citations

Electrical Engineering, Engineering, Power Ic +15

A 8.8-ns 54×54-bit multiplier using new redundant binary architecture

Hiroshi Makino, Y. Nakase, Hirofumi Shinohara · 2002 · 27 citations

Electrical Engineering, Engineering, Vlsi Design +10