Hiroshi Makino

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

S. Ohbayashi, Makoto Yabuuchi, Koji Nii et al. · IEEE Journal of Solid-State Circuits · 2007 · 150 citations

System On Chip, Electrical Engineering, Local Variability +10

An 8.8-ns 54×54-bit multiplier with high speed redundant binary architecture

Hiroshi Makino, Y. Nakase, Hajime Suzuki et al. · IEEE Journal of Solid-State Circuits · 1996 · 134 citations

Low-power Electronics, Hardware Security, Electrical Engineering +12

A low power SRAM using auto-backgate-controlled MT-CMOS

Koji Nii, Hiroshi Makino, Yoshiki Tujihashi et al. · 1998 · 115 citations · Full text

Hardware Security, Low-power Electronics, Electrical Engineering +11

A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment

Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto et al. · 2008 · 110 citations

Hardware Security, Non-volatile Memory, Electrical Engineering +13

Leading-zero anticipatory logic for high-speed floating point addition

Hajime Suzuki, H. Morinaka, Hiroshi Makino et al. · IEEE Journal of Solid-State Circuits · 1996 · 109 citations

Fadd Core, Logic Synthesis, Real Data Type +12