2022 IEEE International Reliability Physics Symposium (IRPS) · 2022 · 10 citations · 6 references
EngineeringElectrical EngineeringPhysicsMicroelectronicsPlasma PhysicsSemiconductor DevicesWell Test AnalysisWell Test DesignPlasma-induced DamagePlasma-induced Degradation
In this paper, a new failure model that explains the plasma-induced damage (PID) involving two wells is described. Contrary to common explanation that the larger wells discharge and damage devices in smaller wells, we propose that the damage is caused by an imbalance of the "RC" associated with each "well system". The victim gate can reside in either the large or small well. This RC imbalance model is supported by the results of various test patterns designed in a 0.13um BCD (Bipolar-CMOS-DMOS) process using NBL (N-type Buried Layer). New design rules have been developed based on the test pattern results.
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Shih‐Hung Chen, Ming-Dou Ker, Hsiang-Pin Hung · IEEE Transactions on Device and Materials Reliability · 2008 · 29 citations