IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2020 · 75 citations · 19 references
EngineeringComputer EngineeringElectrical EngineeringFault ToleranceMicroelectronicsSemiconductor DevicesCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyDevice ReliabilityMemory DevicesRadiation HardeningSemiconductor ReliabilityCmos ReliabilityFailure ProbabilityPower ConsumptionRadiation-hard DevicesRadiation-hardened MemoryRadiation-hardened Memory DevicesRadiation-hardening TechniquesStatic Power Reduction
In this brief, we proposed, based on the polarity upset mechanism of single-event transient voltage of n-channel metal-oxide-semiconductor (nMOS) transistors, a novel radiation hardened by polar design (RHPD) 12T SRAM cell to enhance the reliability and operation speed for space applications. Simulation results in Semiconductor Manufacturing International Corporation (SMIC) 65-nm CMOS commercial standard process show that the proposed RHPD-12T cell can tolerate all single-node upsets. Meanwhile, compared with We-QUATRO, QUATRO, and dual interlocked storage cell (DICE), the write speed of the proposed cell can be reduced by ~41.8 and ~35.3%, and the static power consumption is reduced by ~41.6 and ~46.3%, respectively. Monte Carlo (MC) simulation has proved that under high frequency and low supply (0.6 V) voltage, RHPD-12T has the minimum write failure probability compared with five other SRAM cells.
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