A Comprehensive Study of a Single-Transistor Latch in Vertical Pillar-Type FETs With Asymmetric Source and Drain

Concepts

EngineeringComputer EngineeringElectrical EngineeringMemoryMicroelectronicsSemiconductor DevicesDevice ModelingMemory DevicesMetal-oxide-semiconductor Field-effect TransistorsAsymmetrical LatchDynamic Random-access MemoryDynamic Random-access Memory DesignIon Implantation EffectsLatch DesignLatch TechniqueLow-energy Ion ImplantationRandom-access Memory

Abstract

The single-transistor latch in vertical pillar-type FETs with asymmetric source and drain (S/D) was investigated for capacitorless one transistor dynamic random access memory (1T-DRAM). The asymmetric S/D is produced by the different energies of ion implantation at different depths of the pillar. The window of latch voltage (Δ V L ), which is the difference between the latch-up voltage ( V LU ) and latch-down voltage ( V LD ), was dominantly governed by V LD . Fluctuation in the Δ V L (= V LU - V LD ) is mainly induced by different series resistances ( R SD ). The variation in R SD becomes increasingly fatal to the stable operation of a 1T-DRAM with a smaller diameter; therefore, uniform control of R SD is very important for the read operation in 1T-DRAM. In addition, the doping concentration of the source should be high for wide Δ V L .

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