Scaling trends and bias dependence of the soft error rate of 16 nm and 7 nm FinFET SRAMs

Abstract

SRAM SER measurements across technology nodes indicate that while scaling from planar to the first FinFET process provided a large reduction in per-bit SER, the subsequent scaling within FinFET process nodes results in SER reduction comparable to per-bit cell area reduction. Extensive SER measurements over a range of voltages show a strong exponential increase in the SER of FinFET processes with reduction in bias, compared to a linear bias dependence for the planar process.