On fault tolerance techniques towards nanoscale circuits and systems

Abstract

The move towards nanoscale circuits poses new challenges to circuit design. As the dimensions shrink, it is becoming increasingly difficult to control the variance of physical parameters in the manufacturing process, for instance the concentration of dopants, the thickness of the gate and the insulation oxides, the width and thickness of metal wires, etc. This results in decreased yield which increases the costs per functioning chip. Electromigration causes intermittent and permanent failures after some period of operation, which means that these faults cannot be observed in the manufacture test. The problem of electromigration increases when going further to nanometer regime because of the decreasing width and increasing deviation of wires. Lowering the supply voltages make the circuits more vulnerable to noise and background radiation resulting in a higher soft error rate. The only reasonable way to cope with these reliability problems is to build the circuits fault tolerant. Therefore, the yield can be maintained at an acceptable level by admitting some amount of faults in a chip. Electromigration problems can be