Performance Improvements by SL-Current Limiter and Novel Programming Methods on 16MB RRAM Chip

Abstract

A 16Mb RRAM Chip with source line (SL) current limitation and a novel programming strategy is developed. Comparing with traditional gate control current method, SET operation with source current control can significantly narrow the read current distribution. The programming strategy is optimized simultaneously using a low current multi-step forming and single pulse program operation. With these optimizations, the raw bit yield is improved to 99.99%. Meanwhile the devices on the chip showed good endurance up to 106 cycles without degradation. After 106 cycles the bit error rate of the array is still less than 0.2%. The chip also showed 10 years' retention at 85°C.