A 0.5V 4Mb logic-process compatible embedded resistive RAM (ReRAM) in 65nm CMOS using low-voltage current-mode sensing scheme with 45ns random read time

Abstract

Numerous low-supply-voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ) mobile chips, such as energy-harvesting-powered devices and biomedical applications, require low-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> on-chip nonvolatile memory (NVM) for low-power active-mode access and power-off data storage. However, conventional NVMs cannot achieve low-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> operation due to insufficient write voltage generated by charge-pumped (CP) circuits at a low V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> , and a lack of low-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> current-mode sense amplifiers (CSA) [1-4] to overcome read issues in reduced sensing margins, degraded speeds, and insufficient voltage headroom (VHR). Resistive RAM (ReRAM) [4-6] is a promising memory with the advantages of short write time, low write-voltage, and reduced write power compared to Flash and other NVMs. Using a low-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> CP with relaxed output voltage/current requirements for write operations, ReRAM is a good candidate for on-chip low-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> NVM if a low-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> CSA is provided, particularly for frequent-read-seldom-write applications. We develop a body-drain-driven CSA (BDD-CSA) with dynamic BL bias voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BL</sub> ) and small VHR for larger sensing margins to achieve a lower V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDmin</sub> , faster read speed, and better tolerance of read cell current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">CELL</sub> ) and BL leakage current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BL-LEAK</sub> ) variations compared to conventional CSAs. A fabricated 65nm 4Mb ReRAM macro using the BDD-CSA and our CMOS-logic-compatible ReRAM cell [7] achieves 0.5V V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDmin</sub> . The BDD-CSA achieves 0.32V V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DDmin</sub> .