Characterization of Extreme Si Thinning Process for Wafer-to-Wafer Stacking

Abstract

Wafer-to-wafer 3D integration has a potential tominimize the Si thickness, which enables us to connectmultiple wafers with significantly scaled through-Si vias. Inorder to achieve this type of 3D structure, backside thinningis a key step. Conventional mechanical grinding is known asthe best way to remove bulk Si in terms of cost of ownership(CoO). However, mechanical damage such as induceddislocations needs to be removed after extreme thinning toavoid a serious impact on the device performance. CMPshows the best performance in terms of roughness with asignificantly flat surface with only atomic step roughness. Furthermore, the existing mono-vacancies are as low as for abulk Si substrate. However the total thickness variation(TTV) worsens as more Si is removed. The dry etch processenables a faster etch rate than CMP and wet etching. Furthermore, the mono-vacancy/damage layer after dryetching is equivalent to that achieved when combined withCMP. The combination of CMP and dry etch enables us toachieve extreme thinning of active device wafers (