Effect of annealing process on the surface roughness in multiple Al implanted 4H-SiC

Abstract

A P-layer can be formed on a SiC wafer surface by using multiple Al ion implantations and post-implantation annealing in a low pressure CVD reactor. The Al depth profile was almost box shaped with a height of1×1019cm-3 and a depth of550 nm. Three different annealing processes were developed to protect the wafer surface. Variations in RMS roughness have been measured and compared with each other. The implanted SiC, annealed with a carbon cap, maintains a high-quality surface with an RMS roughness as low as3.8 nm. Macrosteps and terraces were found in the SiC surface, which annealed by the other two processes(protect in Ar/protect with SiC capped wafer in Ar). The RMS roughness is12.2 nm and6.6 nm, respectively.?2011 Chinese Institute of Electronics.