A dependable power grid optimization algorithm considering NBTI timing degradation

Abstract

Reliability becomes one of the most important issues for designing LSIs. Negative bias temperature instability (NBTI) is a phenomenon in which performance of transistors deteriorates depending on temperature and transistor switching frequency. In the manufacturing process generations of 32 nm and 22 nm, it will be expected that timing degradation by NBTI becomes non-ignorable. This research proposes the high reliable power grid optimization technique in which timing degradation by NTBI of after-manufacture five or ten years was taken into consideration.