Bipul C. Paul - Concepedia

Author

Bipul C. Paul

Purdue University West Lafayette

Also Known As

B Paul, B. C. PAUL, B. C. Paul, B. Paul, B.C. Paul, Bidyarthi Paul, Bipul C. Paul, Bipul Paul, Paul, Bidyarthi

100

Publications

4.1K

Citations

H-Index

105

Concepts

All Affiliations

Purdue University West Lafayette Toshiba (United States)Stanford University Toshiba (Japan)Stanford SystemX Alliance

About

Bipul C. Paul is an author at Purdue University West Lafayette specializing in engineering, electrical engineering, and microelectronics.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	31	50	3.9K
2	Applied Physics	19	23	1.9K
3	Business	2	2	61
4	Natural Sciences	2	2	58
5	Chemical Engineering	2	2	49

Bipul C. Paul

Publications

Citations

H-Index

Page 1

	Year	Citations
Circuit Failure Prediction and Its Application to Transistor Aging Mridul Agarwal, Bipul C. Paul, Ming Zhang, Proceedings - IEEE VLSI Test Symposium/Proceedings of the ... IEEE VLSI Test Symposium EngineeringVlsi DesignComputer ArchitectureCircuit FailureHardware Security	2007	444
Robust subthreshold logic for ultra-low power operation H. Soeleman, Kaushik Roy, Bipul C. Paul IEEE Transactions on Very Large Scale Integration (VLSI) Systems Low-power ElectronicsHardware SecurityElectrical EngineeringDesign SpectrumVlsi Design	2001	287
Impact of NBTI on the temporal performance degradation of digital circuits Bipul C. Paul, Kunhyuk Kang, Haldun Küflüoğlu, IEEE Electron Device Letters EngineeringVlsi DesignComputer ArchitectureHardware SecurityNanoelectronics	2005	285
Modeling and Optimization of Fringe Capacitance of Nanoscale DGMOS Devices Aditya Bansal, Bipul C. Paul, Kaushik Roy IEEE Transactions on Electron Devices Device ModelingElectrical EngineeringNanoscale SystemEngineeringVlsi Design	2005	205
A process-tolerant cache architecture for improved yield in nanoscale technologies Amit Agarwal, Bipul C. Paul, Hamid Mahmoodi, IEEE Transactions on Very Large Scale Integration (VLSI) Systems Non-volatile MemoryEngineeringEmerging Memory TechnologyComputer ArchitectureHardware Security	2005	198
A 1 GHz Integrated Circuit with Carbon Nanotube Interconnects and Silicon Transistors Gael F. Close, Shinichi Yasuda, Bipul C. Paul, Nano Letters Electrical EngineeringEngineeringHigh SpeedHigh-frequency DeviceNanoelectronics	2008	192
Process variation in embedded memories: failure analysis and variation aware architecture Amit Agarwal, Bipul C. Paul, Saibal Mukhopadhyay, IEEE Journal of Solid-State Circuits EngineeringVlsi DesignProcess VariationMem TestingComputer Architecture	2005	173
Temporal Performance Degradation under NBTI: Estimation and Design for Improved Reliability of Nanoscale Circuits Bipul C. Paul, Kunhyuk Kang, Haldun Küflüoğlu, Temporal Reliability DegradationEngineeringVlsi DesignThreshold Voltage DegradationComputer Architecture	2006	156
Novel sizing algorithm for yield improvement under process variation in nanometer technology Seung Hoon Choi, Bipul C. Paul, Kaushik Roy EngineeringVlsi DesignProcess VariationIndustrial EngineeringPower Optimization (Eda)	2004	150
Optimized Circuit Failure Prediction for Aging: Practicality and Promise Manu Agarwal, Varsha Balakrishnan, Anshuman Bhuyan, EngineeringVlsi DesignFlip-flop DesignsComputer ArchitectureHardware Security	2008	140

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