Amit Agarwal

Near-threshold voltage (NTV) design

Himanshu Kaul, Mark Anders, Steven Hsu et al. · 2012 · 240 citations

Low-power Electronics, Energy Consumption, Electrical Engineering +11

16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS

Sanu Mathew, Sudhir Satpathy, Mark Anders et al. · 2014 · 237 citations

Hardware Security, Low-power Electronics, Electrical Engineering +14

Reducing set-associative cache energy via way-prediction and selective direct-mapping

Michael D. Powell, Amit Agarwal, T. N. Vijaykumar et al. · International Symposium on Microarchitecture · 2001 · 230 citations

Power-aware Computing, Engineering, Energy Efficiency +13

A process-tolerant cache architecture for improved yield in nanoscale technologies

Amit Agarwal, Bipul C. Paul, Hamid Mahmoodi et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2005 · 198 citations

Non-volatile Memory, Engineering, Emerging Memory Technology +18

2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors

Sanu Mathew, Suresh Srinivasan, Mark Anders et al. · IEEE Journal of Solid-State Circuits · 2012 · 188 citations

Low-power Electronics, Electrical Engineering, Engineering +10