Amit Agarwal

16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS

Sanu Mathew, Sudhir Satpathy, Mark Anders et al. · 2014 · 241 citations

Engineering, Computer Engineering, Electrical Engineering +17

Near-threshold voltage (NTV) design

Himanshu Kaul, Mark Anders, Steven Hsu et al. · 2012 · 241 citations

Engineering, Electrical Engineering, Low-power Design +16

Reducing set-associative cache energy via way-prediction and selective direct-mapping

Michael D. Powell, Amit Agarwal, T. N. Vijaykumar et al. · 2001 · 231 citations · Full text

Engineering, Computer Engineering, Computer Science +17

A process-tolerant cache architecture for improved yield in nanoscale technologies

Amit Agarwal, Bipul C. Paul, Hamid Mahmoodi et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2005 · 199 citations

Engineering, Computer Engineering, Electrical Engineering +17

2.4 Gbps, 7 mW All-Digital PVT-Variation Tolerant True Random Number Generator for 45 nm CMOS High-Performance Microprocessors

Sanu Mathew, Suresh Srinivasan, Mark Anders et al. · IEEE Journal of Solid-State Circuits · 2012 · 190 citations

Engineering, Computer Engineering, Electrical Engineering +17