NBTI impact on transistor and circuit: models, mechanisms and scaling effects [MOSFETs]

Abstract

We describe a quantitative relationship between I/sub D/ and V/sub T/ driven NBTI specifications. Mobility degradation is shown to be a significant (/spl sim/40%) contributor to I/sub D/ degradation. We report for the first time, degradation in gate-drain capacitance (C/sub GD/) due to NBTI. The impact of this C/sub GD/ degradation on circuit performance is quantified for both digital and analog circuits. We find that C/sub GD/ degradation has a greater impact on the analog circuit studied than the digital circuit. We demonstrate that there is an optimum operating voltage that balances NBTI degradation against transistor voltage headroom. Further, a numerical model based on the reaction-diffusion theory has been developed, which is found to satisfactorily describe degradation, recovery and post-recovery response to stress.