Compact thermal modeling of hot spots in advanced 3D-stacked ICs

Abstract

This paper presents a new generic methodology used to determine a parameterized compact thermal model for 3-D stacked integrated circuits (3D-SIC). The method allows to calculate the thermal distribution due to hot spots in the die stack. This approach is applied to different case studies of stacked dies configurations. In order to demonstrate the method, a fully generic non-uniform heat sources ¿grid¿ with grid size of 100 ¿m has been considered. With this approach it is possible to derive an easy-to-use, fast prediction tool that, together with a user friendly graphical interface, allows to obtain the temperature distribution in the dies with good accuracy. Parameters such as the structure geometry, the thermal properties of the materials involved and the effects of the presence of a package resistance are investigated. It is demonstrated that this tool can be used for a fast optimization for the structural parameters, thus helping to design a 3-D die stack when a need for thermal management arises.