C. Torregiani

Design Issues and Considerations for Low-Cost 3-D TSV IC Technology

Geert Van der Plas, Paresh Limaye, Igor Loi et al. · IEEE Journal of Solid-State Circuits · 2010 · 308 citations

Engineering, Vlsi Design, 3-D Chip Stacks +17

Silicides and germanides for nano-CMOS applications

J. A. Kittl, Karl Opsomer, C. Torregiani et al. · Materials Science and Engineering B · 2008 · 66 citations

Nano-cmos Applications, Engineering, Nanoelectronics +6

Design issues and considerations for low-cost 3D TSV IC technology

Geert Van der Plas, Paresh Limaye, A. Mercha et al. · 2010 · 61 citations

Engineering, Vlsi Design, Computer Architecture +16

A Comparison of Spike, Flash, SPER and Laser Annealing for 45nm CMOS

Richard Lindsay, B. J. Pawlak, J. A. Kittl et al. · MRS Proceedings · 2003 · 42 citations

Electrical Engineering, Physical Design (Electronics), Engineering +8

Compact thermal modeling of hot spots in advanced 3D-stacked ICs

C. Torregiani, Herman Oprins, Bart Vandevelde et al. · 2009 · 36 citations

Engineering, New Generic Methodology, Computer-aided Design +18