2008 · 10 citations · 9 references
EngineeringElectrical EngineeringMaterials ScienceElectronic MaterialsPackaging DesignSemiconductor DevicesChip PackagingIntegrated Circuit DesignIntegrated Circuit DevicesIntegrated Circuit FabricationInterconnect DesignInterconnect TechnologyBondingDie-to-wafer BondingFlip-chip BondingProcess CostThree-dimensional IntegrationThrough-silicon Via DesignThrough-silicon ViasVia Formation
To prevent potential yield loss, achieve TSV with higher aspect ratio, improve the bonding reliability, and reduce the process cost, a clamped through silicon via (C-TSV) interconnection for stacked chip bonding is proposed and developed in this paper. The metal cap on pad design can not only be a bonding layer for other stacked die on it, but also performs as a protection stopper for blind vias drilled from the wafer backside..
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3D Chip Stacking Technology with Low-Volume Lead-Free Interconnections
Katsuyuki Sakuma, Paul Andry, B. Dang et al. · 2007 · 83 citations