Characterization of VLSI circuit interconnect heating and failure under ESD conditions

Abstract

The high current and ESD effects on VLSI interconnect metallization have been characterized and a model for heating under ESD conditions is presented. It is shown that thermal breakdown occurs when the resistances increase by a factor of >3.6 due to melting of metal lines. After the metal is molten, the thermal stress is required to exceed the fracture strength of the oxide/nitride layers in order for the overlying dielectric to be cracked and an open circuit to take place. The critical failure current is strongly influenced by the metal thickness and thermal capacity. It is shown that for current pulses below the failure threshold, the metal will return to its original solid state with no change in DC resistance, but it will have a lower electromigration lifetime. This is a potential latent failure. The model is applied to derive relations between critical current, line width and pulse width for determining design guidelines for ESD and I/O buffer interconnects.