IEEE Transactions on Electron Devices · 2011 · 26 citations · 34 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignComplementary Metal-oxide-semiconductor TechnologyDevice ModelingDevice ScalingDevice SimulationMetal-oxide-semiconductor Field-effect TransistorsCmos ScalingDoping ProfilesMetal-oxide-semiconductor Field-effect Transistor ModelingMosfet ModelingOperating VoltageSemiconductor Doping ProfilesThreshold VoltageThreshold Voltage Modeling
The performance and threshold voltage variability of quasi-planar bulk MOSFETs are compared against those of conventional bulk MOSFETs, via three-dimensional (3-D) device simulations with gate line-edge roughness and atomistic doping profiles, at 25 nm gate length. The nominal performance of sixtransistor (6-T) SRAM cells is studied via 3-D simulation of full cell structures. Compact (analytical) modeling is used to estimate SRAM cell yields. As compared to conventional bulk CMOS technology, quasi-planar bulk CMOS technology provides for enhanced SRAM cell performance and yield, and hence facilitates reductions in cell area and operating voltage. It also enables a notchless 6-T SRAM cell design which is advantageous for improved lithographic printability and either smaller area or lower standby power, and is projected to achieve 6-sigma cell yields at operating voltages down to <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\sim$</tex></formula> 0.8 V.
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