The effects of boron penetration on p/sup +/ polysilicon gated PMOS devices

Abstract

The penetration of boron into and through the gate oxides of PMOS devices which employ p/sup +/ doped polysilicon gates is studied. Boron penetration results in large positive shifts in V/sub FB/, increased PMOS subthreshold slope and electron trapping rate, and decreased low-field mobility and interface trap density. Fluorine-related effects caused by BF/sub 2/ implantations into the polysilicon gate are shown to result in PMOS threshold voltage instabilities. Inclusion of a phosphorus co-implant or TiSi/sub 2/ salicide prior to gate implantation is shown to minimize this effect. The boron penetration phenomenon is modeled by a very shallow, fully-depleted p-type layer in the silicon substrate close to the SiO/sub 2//Si interface. >