L.C. Parrillo - Concepedia

Author

L.C. Parrillo

Motorola (United States)

Also Known As

L. C. Parrillo, L. Parrillo, L.C. Parrillo, Louis C. Parrillo

Publications

606

Citations

H-Index

Concepts

All Affiliations

Motorola (United States)AT&T (United States)

About

L.C. Parrillo is an author at Motorola (United States) specializing in applied physics, microelectronics, and electrical engineering.

Top Concepts

#	Concept	H-Index	Publications	Citations
1	Engineering	11	15	550
2	Applied Physics	11	13	528
3	Electrical Engineering	11	14	522
4	Computer Engineering	5	5	125
5	Chemical Engineering	1	1	11

L.C. Parrillo

Publications

550

Citations

H-Index

Page 1

	Year	Citations
The effects of boron penetration on p/sup +/ polysilicon gated PMOS devices J.R. Pfiester, F.K. Baker, T.C. Mele, IEEE Transactions on Electron Devices Electrical EngineeringPolysilicon GateEngineeringNanoelectronicsBias Temperature Instability	1990	211
Twin-tub CMOS - A technology for VLSI circuits L.C. Parrillo, Robert Payne, R.E. Davis, EngineeringVlsi DesignN-channel TransistorsComputer ArchitectureIntegrated Circuits	1980	61
The influence of fluorine on threshold voltage instabilities in p/sup +/ polysilicon gated p-channel MOSFETs F.K. Baker, J.R. Pfiester, T.C. Mele, Threshold Voltage InstabilitiesSemiconductor TechnologyElectrical EngineeringEngineeringP-channel Mosfets	2003	54
A physical model for boron penetration through thin gate oxides from p/sup +/ polysilicon gates J.R. Pfiester, L.C. Parrillo, F.K. Baker IEEE Electron Device Letters Thin Gate OxidesElectrical EngineeringEngineeringPhysicsPhysical Model	1990	52
Acceptor State of Gold in Silicon—Resolution of an Anomaly L.C. Parrillo, W. C. Johnson Applied Physics Letters SemiconductorsSemiconductor TechnologySevere AnomalyEngineeringPhysics	1972	28
Twin-Tub CMOS II-An advanced VLSI technology L.C. Parrillo, L.K. Wang, R.D. Swenumson, EngineeringVlsi DesignComputer ArchitectureIntegrated CircuitsSemiconductor Device	1982	25
Poly-gate sidewall oxidation induced submicrometer MOSFET degradation J.R. Pfiester, L.C. Parrillo, J.D. Hayden, IEEE Electron Device Letters Device ModelingElectrical EngineeringEngineeringShort-channel Mosfet BehaviorNanoelectronics	1989	22
A fine-line CMOS technology that uses p<sup>+</sup>polysilicon/silicide gates for NMOS and PMOS devices L.C. Parrillo, S.J. Hillenius, Ryan Field, Pmos TransistorsElectrical EngineeringEngineeringVlsi DesignApplied Physics	1984	16
The reduction of emitter-collector shorts in a high-speed all-implanted bipolar technology L.C. Parrillo, Robert Payne, Thomas E. Seidel, IEEE Transactions on Electron Devices Low-power ElectronicsDefect ToleranceElectrical EngineeringOxygen ConcentrationEngineering	1981	14
A high-performance sub-half micron CMOS technology for fast SRAMs J.D. Hayden, F.K. Baker, Stephen Ernst, EngineeringVlsi DesignComputer ArchitectureIntegrated CircuitsAdvanced Packaging (Semiconductors)	2003	13

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