L.C. Parrillo

The effects of boron penetration on p/sup +/ polysilicon gated PMOS devices

J.R. Pfiester, F.K. Baker, T.C. Mele et al. · IEEE Transactions on Electron Devices · 1990 · 211 citations

Electrical Engineering, Polysilicon Gate, Engineering +13

Twin-tub CMOS - A technology for VLSI circuits

L.C. Parrillo, Robert Payne, R.E. Davis et al. · 1980 · 61 citations

Engineering, Vlsi Design, N-channel Transistors +16

The influence of fluorine on threshold voltage instabilities in p/sup +/ polysilicon gated p-channel MOSFETs

F.K. Baker, J.R. Pfiester, T.C. Mele et al. · 2003 · 54 citations

Threshold Voltage Instabilities, Semiconductor Technology, Electrical Engineering +12

A physical model for boron penetration through thin gate oxides from p/sup +/ polysilicon gates

J.R. Pfiester, L.C. Parrillo, F.K. Baker · IEEE Electron Device Letters · 1990 · 52 citations

Thin Gate Oxides, Electrical Engineering, Engineering +14

Acceptor State of Gold in Silicon—Resolution of an Anomaly

L.C. Parrillo, W. C. Johnson · Applied Physics Letters · 1972 · 28 citations

Semiconductors, Semiconductor Technology, Severe Anomaly +14