Robert Payne

A 6.25-Gb/s binary transceiver in 0.13-/spl mu/m CMOS for serial data transmission across high loss legacy backplane channels

Robert Payne, P. Landman, B. Bhakta et al. · IEEE Journal of Solid-State Circuits · 2005 · 102 citations

Engineering, Vlsi Design, Speculative Techniques +15

Twin-tub CMOS - A technology for VLSI circuits

L.C. Parrillo, Robert Payne, R.E. Davis et al. · 1980 · 61 citations

Engineering, Vlsi Design, N-channel Transistors +16

Elimination of latch up in bulk CMOS

Robert Payne, W.N. Grant, W.J. Bertram · 1980 · 58 citations

Engineering, Vlsi Design, Computer Engineering +4

Fully ion-implanted bipolar transistors

Robert Payne, R. J. Scavuzzo, Kevin Olson et al. · IEEE Transactions on Electron Devices · 1974 · 51 citations

Semiconductors, Semiconductor Technology, Electrical Engineering +13

A 6.25Gb/s binary adaptive DFE with first post-cursor tap cancellation for serial backplane communications

Robert Payne, B. Bhakta, S. Ramaswamy et al. · 2005 · 46 citations

Engineering, Vlsi Design, Mixed-signal Integrated Circuit +8