IEEE Transactions on Nanotechnology · 2011 · 14 citations · 13 references
EngineeringElectrical EngineeringMaterials ScienceMicroelectronicsSemiconductor DevicesSemiconductor MaterialsDevice ModelingIntegrated Circuit DesignMemory DevicesMemory Subsystem DesignDynamic Random-access MemoryDynamic Random-access Memory DesignHigh-density Storage SystemsMemory Cell DesignMemory Circuit DesignRandom Access Memory (Ram)Superlattice Materials
We propose a novel SiGe superlattice bandgap-engineered (SBE) capacitorless dynamic random access memory (DRAM) cell with 30-nm channel length as a next-generation DRAM cell with high storage density and long retention time for practical implementation by 2-D technology computer-aided design simulation. The SBE capacitorless DRAM cell uses a common source structure and different metal layers for the top gate word line (WL) from the bottom gate WL to realize a 6F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> feature size. Thanks to the Si <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.8</sub> Ge <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.2</sub> superlattice quantum well and silicon dioxide (SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) physical barrier, we obtained 213 μA/μm for the sensing margin and about 10 ms for the retention time.
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Defects in epitaxial multilayers
J. W. Matthews, A. E. Blakeslee · Journal of Crystal Growth · 1976 · 594 citations
A SOI capacitor-less 1T-DRAM concept
S. Okhonin, M. Nagoga, J.-M. Sallese et al. · 2002 · 141 citations
Engineering, Computer Engineering, Electrical Engineering +14