IEEE Electron Device Letters · 2003 · 11 citations · 4 references
EngineeringComputer EngineeringElectrical EngineeringElectronic MaterialsMicroelectronicsSemiconductor DevicesDevice ModelingDevice ScalingDevice SimulationMemory DevicesNanoelectronicsShort-channel EffectsDevice Scaling EffectsDimensional ScalingFlash MemoryFlash Memory DevicesFloating-gate MemoryFowler-nordheim TunnelingNon-volatile Memory DesignParasitic Capacitance
In this letter, new limitations on the NOR flash cell scaling have been presented. As cell scaling is continued, a parasitic capacitance between floating gate and bitline contact induces a large disturbance to the Fowler-Nordheim tunneling characteristics due to a coupling ratio variation, resulting in a much broader erase threshold distribution. Theoretical analysis including MEDICI simulations confirms the effects of parasitic capacitance on the erase threshold of NOR flash cells.
4
Analysis and modeling of floating-gate EEPROM cells
Avinoam Kolodny, S. T. K. Nieh, B. Eitan et al. · IEEE Transactions on Electron Devices · 1986 · 178 citations