Concepedia

S. Muramatsu

SM

4

Publications

67

Citations

4

H-Index

2002

Active since

Affiliations

NEC (Japan)(Current)

Toshiba (Japan)

S. Muramatsu is an author at NEC (Japan) specializing in microelectronics, electrical engineering, and engineering.

Top concepts

EngineeringMicroelectronicsElectrical EngineeringApplied PhysicsComputer ArchitectureVlsi DesignMicrofabricationComputer Engineering3D Memory3D Printing

Publications per year

2002–2008

4

Publications

4

The solution of over-erase problem controlling poly-Si grain size-modified scaling principles for flash memory

S. Muramatsu, T. Kubota, N. Nishio et al. · 2002 · 24 citations

Non-volatile Memory, Engineering, Memory Design +18

A 45nm High Performance Bulk Logic Platform Technology (CMOS6) using Ultra High NA(1.07) Immersion Lithography with Hybrid Dual-Damascene Structure and Porous Low-k BEOL

H. Nii, T. Sanuki, Y. Okayama et al. · 2006 · 22 citations

Engineering, Ultra High Na, Wafer Scale Processing +16

A cost-conscious 32nm CMOS platform technology with advanced single exposure lithography and gate-first metal gate/high-k process

Shunsuke Hasegawa, Y. Kitamura, Kazuo Takahata et al. · 2008 · 11 citations

Total Cost, Engineering, Vlsi Design +16

Management of Power and Performance with Stress Memorization Technique for 45nm CMOS

A. Eiho, T. Sanuki, E. Morifuji et al. · 2007 · 10 citations

Low-power Electronics, Electrical Engineering, Appropriate Stressor +12

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