Effects of floating-gate interference on NAND flash memory cell operation

Abstract

Introduced the concept of floating-gate interference in flash memory cells for the first time. The floating-gate interference causes V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> shift of a cell proportional to the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> change of the adjacent cells. It results from capacitive coupling via parasitic capacitors around the floating gate. The coupling ratio defined in the previous works should be modified to include the floating-gate interference. In a 0.12-μm design-rule NAND flash cell, the floating-gate interference corresponds to about 0.2 V shift in multilevel cell operation. Furthermore, the adjacent word-line voltages affect the programming speed via parasitic capacitors.