Effects of floating-gate interference on NAND flash memory cell operation

Jae-Duk Lee, Sung‐Hoi Hur, Jungdal Choi

IEEE Electron Device Letters

Non-volatile MemoryElectrical EngineeringFlash Memory CellsEngineeringVlsi Design +11

Charge-trapping device structure of SiO2∕SiN∕high-k dielectric Al2O3 for high-density flash memory

Chang‐Hyun Lee, Sung‐Hoi Hur, You-Cheol Shin, +3

Applied Physics Letters

Non-volatile MemoryEngineeringHigh-density Flash MemorySio2∕sin∕high-k Dielectric Al2o3Charge-trapping Device Structure +14

A physical-based analytical turn-on model of polysilicon thin-film transistors for circuit simulation

Gi-Yong Yang, Sung‐Hoi Hur, Chul‐Hi Han

IEEE Transactions on Electron Devices

EngineeringVlsi DesignCurrent ModelPolysilicon Thin-film TransistorsSemiconductor Device +14

8Gb MLC (Multi-Level Cell) NAND flash memory using 63nm process technology

Jong‐Ho Park, Sung‐Hoi Hur, Joun-Hee Lee, +15

Non-volatile MemoryEngineeringComputer ArchitectureNand Flash Memory3D Memory +15

The new program/erase cycling degradation mechanism of NAND flash memory devices

Albert Fayrushin, Kwang-Soo Seol, J.H. Na, +3

Non-volatile MemoryElectrical EngineeringNand Memory CellsEngineeringEmerging Memory Technology +13

An 8gb multi-level NAND flash memory with 63nm STI CMOS process technology

Dae-Seok Byeon, Sungsoo Lee, Young-Ho Lim, +15

Non-volatile MemoryElectrical EngineeringMemory ArchitectureEngineeringFlash Memory +7

13.3 A 280-Layer 1Tb 4b/cell 3D-NAND Flash Memory with a 28.5Gb/mm2 Areal Density and a 3.2GB/s High-Speed IO Rate

Wontaeck Jung, Hyung-Gon Kim, Do-Bin Kim, +51

Hardware SecurityKey DeviceElectrical EngineeringNon-volatile MemoryEngineering +13

A 3.3 V 4 Gb four-level NAND flash memory with 90 nm CMOS technology

Seungjae Lee, Young-Taek Lee, Wook-Kee Han, +10

Hardware SecurityNon-volatile MemoryElectrical EngineeringEngineeringNm Cmos +12

Highly reliable polysilicon oxide grown by electron cyclotron resonance nitrous oxide plasma

Nae-In Lee, Jinwoo Lee, Sung‐Hoi Hur, +2

IEEE Electron Device Letters

Materials ScienceMaterials EngineeringElectrical EngineeringNon-volatile MemoryEngineering +11

Highly Reliable Cell Characteristics with CSOB(Channel-hole Sidewall ONO Butting) Scheme for 7th Generation 3D-NAND

Jin-Kyu Kang, Jae-Duk Lee, Yong-Sik Yim, +11

2021 IEEE International Electron Devices Meeting (IEDM)

Hardware SecurityNon-volatile MemoryElectrical Engineering3D Ic ArchitectureEngineering +10