High throughput flip chip processing and reliability analysis using no-flow underfills

Abstract

As a concept to achieve high throughput low cost flip chip on board (FCOB) assembly, a process development activity is underway, implementing next generation flip chip processing based on large area underfill printing/dispensing, integrated chip placement and underfill flow, and simultaneous solder interconnect reflow and underfill cure. Reported in this work is the assembly of a series of test vehicles to assess process yield, process defects, and the reliability of no-flow underfill materials. Critical process design models are presented to predict chip motion during and after the chip placement process, enabling design of the placement process and underfill volume/mass to ensure high yields. Also reported are the results of reliability testing based on air to air and liquid to liquid thermal cycling.