[110] strained-SOI n-MOSFETs with higher electron mobility

Abstract

We have recently developed [110]-surface strained silicon-on-insulator (SOI) n-MOSFETs. The strained-silicon (Si) layer with the strain of about 0.6% has been fabricated on a relaxed SiGe-on-insulator (SGOI) structure with the germanium (Ge) content of 25%. The electron mobility characteristics along the various current directions have been experimentally studied and compared to those of [100]- and [110]-surface unstrained-bulk MOSFETs. We have demonstrated, for the first time, that the electron mobility of [110] strained-SOI MOSFETs is enhanced, compared to that of [110] unstrained-bulk MOSFETs. The electron mobility enhancement depends on the current-flow directions, and the maximum enhancement factor amounts to 23% along the <001> direction. As a result, the electron mobility ratio of [110] strained-SOI MOSFETs to [100] universal mobility is 81% at maximum, whereas the ratio of [110] unstrained-bulk MOSFETs is only 66%. Therefore, [110] strained-SOI devices are also promising candidates for future high-performance CMOS.