IEEE Journal of Solid-State Circuits · 2003 · 97 citations · 13 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureLow-power DesignMicroelectronicsCmos Circuit DesignDynamic Power ReductionIntegrated Circuit DesignInterconnect DesignLeakage Power ReductionProcessor Core DesignDynamic Cmos LogicLow-power AddersLow-power Cmos DesignLow-power Interconnect DesignLow-voltage Cmos DesignStatic Cmos CircuitsStatic Cmos LogicUltra-low-power Cmos
This paper describes a 32-bit address generation unit designed for 4-GHz operation in 1.2-V 130-nm technology. The AGU utilizes a 152-ps sparse-tree adder core to achieve 20% delay reduction, 80% lower interconnect complexity, and a low (1%) active energy leakage component. The dual-V/sub T/ semidynamic implementation of the adder core provides the performance of a dynamic CMOS design with an average energy profile similar to static CMOS, enabling 71% savings in average energy with a good sub-130-nm scaling trend.
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