Dynamic Cmos Logic

Dynamic CMOS Logic is a type of complementary metal-oxide-semiconductor (CMOS) logic circuit that operates in two distinct phases—precharge and evaluation—using a clocked pulldown or pull-up network to conditionally discharge a precharged node, thereby enabling high-speed, low-power operation through temporary storage of logic values on parasitic capacitances.

61

Publications

3.5K

Citations

164

Authors

61

Institutions

Publications per year

2017–2026

5

Variants

Dynamic Cmos

Authors

164

  1. MY
    M. YOKOYAMA

    Okayama University, Japan

    4 publications · 92 citations

    4

    h-index

  2. MM
    Mitsuru Mizunuma

    Yamagata University, Japan

    3 publications · 78 citations

    3

    h-index

  3. JW
    Jinn‐Shyan Wang

    National Chung Cheng University, Taiwan

    3 publications · 126 citations

    3

    h-index

  4. KT
    Kazukiyo Takahashi

    Yamagata University, Japan

    3 publications · 77 citations

    3

    h-index

  5. YT
    Yasuhiro Takahashi

    Gifu University, Japan

    3 publications · 81 citations

    3

    h-index

1–5 of 164

Venues

  1. IEEE Journal of Solid-State Circuits

    10 publications · 1.3K citations

    10

    h-index

  2. 3

    h-index

  3. 3

    h-index

  4. 3

    h-index

  5. Electronics Letters

    2 publications · 27 citations

    2

    h-index

1–5