Dynamic Cmos Logic
Dynamic CMOS Logic is a type of complementary metal-oxide-semiconductor (CMOS) logic circuit that operates in two distinct phases—precharge and evaluation—using a clocked pulldown or pull-up network to conditionally discharge a precharged node, thereby enabling high-speed, low-power operation through temporary storage of logic values on parasitic capacitances.
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3.5K
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164
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61
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2017–2026
5
Variants
Dynamic Cmos
Parents
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Kris Tiri, Muhammad Akmal, Ingrid Verbauwhede · European Solid-State Circuits Conference · 2002 · 518 citations
Engineering, Computer Engineering, Electrical Engineering +17
Semi-dynamic and dynamic flip-flops with embedded logic
F. Klass · 2002 · 151 citations
Engineering, Computer Engineering, Electrical Engineering +12
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National Chung Cheng University
Minxiong, Taiwan
4 h-index
10 publications
465 citations

National Sun Yat-sen University
Kaohsiung City, Taiwan
3 h-index
10 publications
413 citations

National Institute of Astrophysics, Optics and Electronics
Puebla City, Mexico
2 h-index
6 publications
134 citations

Sapienza University of Rome
Rome, Italy
2 h-index
9 publications
144 citations

Bar-Ilan University
Ramat Gan, Israel
2 h-index
3 publications
52 citations
KU Leuven
Leuven, Belgium
2 h-index
5 publications
699 citations

University of Calabria
Rende, Italy
2 h-index
6 publications
174 citations
Texas Instruments (United States)
Dallas, United States
2 h-index
3 publications
265 citations
1–8 of 61
10 publications · 1.3K citations
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3 publications · 120 citations
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3 publications · 59 citations
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3 publications · 360 citations
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2 publications · 27 citations
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