R. Bigwood

A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm/sup 2/ SRAM cell

Scott E. Thompson, N. Anand, M Armstrong et al. · 2003 · 241 citations

Nm Logic Technology, Engineering, Vlsi Design +19

A 130 nm generation logic technology featuring 70 nm transistors, dual Vt transistors and 6 layers of Cu interconnects

S. Tyagi, Morteza S. Alavi, R. Bigwood et al. · 2002 · 149 citations

Engineering, Vlsi Design, Dual Vt Transistors +16

An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7 - 1.4 V

Scott E. Thompson, Morteza S. Alavi, Reza Arghavani et al. · 2002 · 62 citations

Low-power Electronics, Low Power, Electrical Engineering +15

Low-k interconnect stack with a novel self-aligned via patterning process for 32nm high volume manufacturing

R. Brain, S. Agrawal, D. Becher et al. · 2009 · 34 citations

Engineering, Computer Architecture, Interconnect (Integrated Circuits) +19

Lithography strategy for 65-nm node

Yan Borodovsky, Richard E. Schenker, Gary Allen et al. · Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE · 2002 · 13 citations

Materials Science, Engineering, Beam Lithography +14