Low-power Adders

Low-Power Adders is a class of digital arithmetic circuits designed to perform binary addition with minimized power consumption, distinguished from conventional adders by their optimization for energy efficiency through techniques such as reduced voltage swing, glitch reduction, and transistor-level design enhancements.

697

Publications

27.6K

Citations

1.6K

Authors

510

Institutions

Publications per year

2017–2026

214

Authors

1.6K

  1. KN
    Keivan Navi

    Shahid Beheshti University, Iran

    22 publications · 879 citations

    16

    h-index

  2. MB
    Magdy Bayoumi

    University of Louisiana at Lafayette, United States

    14 publications · 1K citations

    12

    h-index

  3. MH
    Mohammad Hossein Moaiyeri

    Shahid Beheshti University, Iran

    11 publications · 451 citations

    11

    h-index

  4. EC
    Eduardo Costa

    Universidade Católica de Pelotas, Brazil

    11 publications · 296 citations

    10

    h-index

  5. KR
    Kaushik Roy

    Purdue University West Lafayette, United States

    12 publications · 1.8K citations

    10

    h-index

1–5 of 1.6K

Venues

  1. 22

    h-index

  2. IEEE Journal of Solid-State Circuits

    18 publications · 838 citations

    14

    h-index

  3. 14

    h-index

  4. Microelectronics Journal

    16 publications · 612 citations

    13

    h-index

  5. Electronics Letters

    11 publications · 478 citations

    11

    h-index

1–5