Low-power Adders
Low-Power Adders is a class of digital arithmetic circuits designed to perform binary addition with minimized power consumption, distinguished from conventional adders by their optimization for energy efficiency through techniques such as reduced voltage swing, glitch reduction, and transistor-level design enhancements.
697
Publications
27.6K
Citations
1.6K
Authors
510
Institutions
Publications per year
2017–2026
214
697
Ning Zhu, Wang Ling Goh, W ZHANG et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2009 · 377 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +15
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510
Shahid Beheshti University
Tehran, Iran
20 h-index
66 publications
2.9K citations
Nanyang Technological University
Singapore, Singapore
17 h-index
50 publications
4.1K citations
Intel (United States)
Santa Clara, United States
13 h-index
32 publications
3K citations
Islamic Azad University, Science and Research Branch
Tehran, Iran
12 h-index
20 publications
700 citations
Purdue University West Lafayette
West Lafayette, United States
11 h-index
45 publications
6.9K citations
The University of Texas at Austin
Austin, United States
11 h-index
20 publications
2.3K citations
Vellore Institute of Technology University
Vellore, India
11 h-index
29 publications
1.3K citations
Islamic Azad University Kerman
Kerman, Iran
10 h-index
17 publications
419 citations
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24 publications · 2.7K citations
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18 publications · 838 citations
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18 publications · 1K citations
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16 publications · 612 citations
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11 publications · 478 citations
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