Static Cmos Logic
Static CMOS Logic is a digital logic family within CMOS circuit design that employs a complementary arrangement of NMOS and PMOS transistors in a pull-down and pull-up network, respectively, to realize logic functions with rail-to-rail voltage swing, high noise immunity, and zero static power dissipation.
229
Publications
8.9K
Citations
571
Authors
189
Institutions
Publications per year
2017–2026
16
Parents
229
Ultra Low-Voltage Low-Power CMOS 4-2 and 5-2 Compressors for Fast Arithmetic Circuits
Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang · IEEE Transactions on Circuits and Systems I Fundamental Theory and Applications · 2004 · 407 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +17
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189
Intel (United States)
Santa Clara, United States
13 h-index
30 publications
2.5K citations
University of Washington
Seattle, United States
11 h-index
27 publications
719 citations
IBM (United States)
Armonk, United States
9 h-index
34 publications
1.6K citations
Purdue University West Lafayette
West Lafayette, United States
9 h-index
15 publications
553 citations
IBM Research - Thomas J. Watson Research Center
Yorktown Heights, United States
8 h-index
14 publications
1K citations

Gifu University
Gifu City, Japan
8 h-index
23 publications
757 citations
Oregon State University
Corvallis, United States
7 h-index
14 publications
785 citations
Carnegie Mellon University
Pittsburgh, United States
6 h-index
8 publications
333 citations
1–8 of 189
24 publications · 1.5K citations
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16 publications · 760 citations
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6 publications · 232 citations
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5 publications · 635 citations
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4 publications · 105 citations
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