Static Cmos Logic

Static CMOS Logic is a digital logic family within CMOS circuit design that employs a complementary arrangement of NMOS and PMOS transistors in a pull-down and pull-up network, respectively, to realize logic functions with rail-to-rail voltage swing, high noise immunity, and zero static power dissipation.

229

Publications

8.9K

Citations

571

Authors

189

Institutions

Publications per year

2017–2026

16

Authors

571

  1. CS
    Carl Sechen

    University of Washington, United States

    10 publications · 279 citations

    10

    h-index

  2. TS
    Toshikazu Sekine

    Gifu University, Japan

    9 publications · 284 citations

    9

    h-index

  3. YT
    Yasuhiro Takahashi

    Gifu University, Japan

    9 publications · 284 citations

    9

    h-index

  4. KR
    Kaushik Roy

    Purdue University West Lafayette, United States

    8 publications · 332 citations

    8

    h-index

  5. GY
    Gin Yee

    University of Washington, United States

    7 publications · 220 citations

    7

    h-index

1–5 of 571

Venues

  1. IEEE Journal of Solid-State Circuits

    24 publications · 1.5K citations

    20

    h-index

  2. 15

    h-index

  3. 6

    h-index

  4. 5

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  5. IEEE Transactions on Nuclear Science

    4 publications · 105 citations

    4

    h-index

1–5