IEEE Electron Device Letters · 2012 · 177 citations · 10 references
EngineeringElectrical EngineeringMicroelectronicsNanotechnologySemiconductor DevicesDevice CharacterizationDevice ScalingDevice SimulationDopingField-effect TransistorsSemiconductor PhysicsChannel Doping EffectsDrain-induced Barrier LoweringFin Field-effect TransistorsLine-edge RoughnessMetal-oxide-semiconductor Field-effect Transistor ModelingRandom Dopant FluctuationTechnological VariabilityThreshold Voltage
Junctionless fin held-effect transistor (FinFET) variability due to random dopant fluctuation (RDF) was investigated for sub-32-nm technology generations using technology computer-aided design (TCAD) simulations. Results indicate that variations in threshold voltage, drive current, leakage current, and drain-induced barrier lowering are heavily impacted by RDF for junctionless FinFETs with sufficiently high channel doping (greater than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> ). Unexpectedly, the RDF impact is found to be less severe for finer technology generations, although the overall magnitude is still significant compared to line-edge-roughness-induced variability.
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Chi‐Woo Lee, Isabelle Ferain, Aryan Afzalian et al. · Solid-State Electronics · 2009 · 556 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +13