IEEE Transactions on Electron Devices · 2008 · 49 citations · 25 references
EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesSemiconductor MaterialsDevice ScalingElectronic Transport ModelingNanoelectronicsSemiconductor InterfacesSemiconductor PhysicsShort-channel EffectsGate-all-around Transistor ScalingMetal-oxide-semiconductor Field-effect Transistor ModelingPhysics-based Device ModelingPotential DistributionSemiconductor Device ModelingShort-channel Scaling TheorySubthreshold ConductionThreshold Voltage Modeling
<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A precise modeling framework for short-channel nanoscale double-gate (DG) and gate-all-around (GAA) MOSFETs is presented. For the DG MOSFET, the modeling is based on a conformal mapping analysis of the potential distribution in the device body arising from the interelectrode capacitive coupling, combined with a self-consistent procedure to include the effects of the inversion charge. The DG interelectrode coupling, which dominates the subthreshold behavior of the device, can also be applied with a high degree of precision to the cylindrical GAA MOSFET by performing a simple geometric scaling transformation to account for the difference in gate control in the two devices. Near threshold, self-consistent procedures invoking Poisson's equation in combination with boundary conditions and suitable modeling expressions for the potential are applied to the two devices. In strong inversion, these solutions converge to those of the respective long-channel devices. The drain current is calculated as part of the self-consistent treatment. The results for both the electrostatics and the current are in excellent agreement with numerical simulations. </para>
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Scaling theory for double-gate SOI MOSFET's
Ken Suzuki, Tetsu Tanaka, Y. Tosaka et al. · IEEE Transactions on Electron Devices · 1993 · 556 citations · Full text
Engineering, Electrical Engineering, Electronic Materials +16