EngineeringComputer EngineeringElectrical EngineeringCircuit TheoryMicroelectronicsSemiconductor DevicesBuilt-in Self-testCmos Circuit DesignDesign For TestabilityMetal-oxide-semiconductor Field-effect TransistorsShort-channel EffectsTiming AnalysisCmos Logic CircuitsCmos ReliabilityPropagation Delay VariabilitySource-drain LeakageStatic Cmos Circuits
This paper studies the effects of shorts within CMOS gates. Dynamic as well as static gate properties are analyzed as a function of the short’s resistance. Increased propagation delay is found to be a common dynamic effect. Circuit behavior can change drastically with small variations in a short’s resistance. It is found that faults caused by transistor gate-to-source and gate-to-drain shorts can be dependent not only on inputs of gates containing the faults but also on other signals. This pattern dependence due to “resistive shorts” can invalidate tests generated using normal TPG procedures.
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Realistic fault modeling for VLSI testing
W. Maly · 1987 · 241 citations
Engineering, Computer Engineering, Electrical Engineering +14
Built-in current testing-feasibility study
W. Maly, P. Nigh · 2003 · 223 citations
Engineering, Computer Engineering, Electrical Engineering +15
Failure mechanisms in semiconductor devices
D.J.S. · Microelectronics Reliability · 1988 · 164 citations