High I/O Glass Ceramic Package PbiFree BGA Interconnect Reliability

Abstract

For high performance computer system applications, there are limitations for reliably and cost effectively attaching high I/O count ceramic packages on thick boards. Moreover, there is a lack of Pb-free solder joint reliability data for large pin count packages in general. To address these limitations and extend ceramic package technology for Pb-free applications, we developed a 2533 I/O HITCE Ceramic Sn/Ag/Cu (SAC) BGA package test vehicle and performed a series of board level solder joint reliability tests. Several package and board design parameters were evaluated to determine their effect on the second level interconnect reliability. This paper presents the test vehicle, board assembly, and solder joint reliability test results. The effect of the package and board design, solder joint reliability for eutectic PbSn vs. SAC, and the package reliable usage space for system applications are discussed.