2002 · 53 citations · 6 references
EngineeringComputer EngineeringElectrical EngineeringFault-tolerant ComputingFault-tolerant SystemsSimulation-based DesignBuilt-in Self-testDesign For TestabilityTiming AnalysisDelay Fault TestingFault CoverageFault Coverage AnalysisFault SimulationLatch DesignScan Chain DesignScan DesignTiming Faults
A problem involving the arrangement of latches in a scan-path design to improve the coverage of delay faults is described. The problem is NP-hard, and a heuristic algorithm is introduced for solving this arrangement problem. A necessary and sufficient condition is also given to determine whether there is a scan path to implement a given delay-fault test pair. Only LAM (latch-arrangement-mapping) implementable test pairs need to be simulated by a delay-fault simulator for a semi-completed LSSD (level-sensitive-scan-design) circuit. Preliminary experimental results show that the proposed algorithm can find a LAM with better fault coverage than a randomly selected ones.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
6
J.A. Waicukauski, Eric Lindbloom, Barry K. Rosen et al. · IEEE Design & Test of Computers · 1987 · 402 citations
Engineering, Computer Engineering, Electrical Engineering +16
Delay test generation. II. Algebra and algorithms
V. Iyengar, Barry K. Rosen, I. Spillinger · 2003 · 59 citations