Concepedia

Boosted and distributed rail clamp networks for ESD protection in advanced CMOS technologies

Michael Stockinger, James W. Miller, Michael G. Khazhinsky, Cynthia A. Torres, James C. Weldon, Bryan D. Preble, M.J. Bayer, M. Akers, Vishnu Kamat

2003 · 93 citations · 10 references

Concepts

EngineeringElectrical EngineeringCircuit TheoryMicroelectronicsCmos Circuit DesignProtection SystemsDistributed Clamp DesignGate Grounded Diode ProtectionProtection CircuitsRail Clamp DesignRcd Clamp Circuits

Abstract

A new, area efficient, boosted and distributed active MOSFET rail clamp network for I/O pad ESD protection is presented. In addition, a compact new rail clamp trigger circuit with high resistance to false triggering is introduced.

References

10

Investigation on different ESD protection strategies devoted to 3.3 V RF applications (2 GHz) in a 0.18 μm CMOS process

C. Richier, P. Salome, G. Mabboux et al. · 2002 · 145 citations

Engineering, Electrical Engineering, Microelectronics +13

An analytical breakdown model for short-channel MOSFET's

Fu-Chieh Hsu, Ping-Keung Ko, Simon Tam et al. · IEEE Transactions on Electron Devices · 1982 · 131 citations

Engineering, Electrical Engineering, Circuit Theory +16

Sub-micron chip ESD protection schemes which avoid avalanching junctions

E. Worley, Ratnesh Gupta, B.E. Jones et al. · 1995 · 110 citations

Engineering, Electrical Engineering, Microelectronics +9

Novel clamp circuits for IC power supply protection

Timothy J. Maloney, S. Dabral · 1995 · 75 citations

Engineering, Electrical Engineering, Microelectronics +16

Multi-finger turn-on circuits and design techniques for enhanced ESD performance and width-scaling

M. Mergens, K. Verhaege, C. Russ et al. · Electrical Overstress/Electrostatic Discharge Symposium · 2001 · 43 citations

Engineering, Electrical Engineering, Microelectronics +12