Electrical Overstress/Electrostatic Discharge Symposium · 2001 · 43 citations · 7 references
EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignDevice ScalingIntegrated Circuit DesignPhysical DesignVery-large-scale Integration LayoutBallastBallast DesignCmos ScalingScaling Effects In CmosTurn-on Mechanisms
A silicon-proven multi-finger turn-on (MFT) design technique that enables ESD width scaling combined with very low dynamic on-resistance is presented in various implementations. It can be applied to (self-protecting) drivers and/or ESD protection design. Using a novel merged ballast circuit design, very compact ESD protection configurations with an ESD area performance up to 5VHBM/um2 can be realized both in fully silicided and silicide blocked NMOS designs.
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Substrate pump NMOS for ESD protection applications
C. Duvvury, S. Ramaswamy, A. Amerasekera et al. · 2002 · 80 citations
Engineering, Computer Engineering, Electrical Engineering +9
The effect of silicide on ESD performance
Guido Notermans, A. Heringa, M. van Dort et al. · 2003 · 41 citations
Engineering, Electrical Engineering, Electronic Materials +16